Publications

2020

34. C. Duran et al., “An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications,” 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020, pp. 1-4, doi: 10.1109/CICC48029.2020.9075877.
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33. W. Ramirez, M. Sarmiento and E. Roa, “A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip,” 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, 2020, pp. 1-4, doi: 10.1109/LASCAS45839.2020.9068995.
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32. R. Torres, L. E. G. Rueda, N. Cuevas and E. Roa, “On the Design of Reliable and Accurate Current References,” 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, 2020, pp. 1-4, doi: 10.1109/LASCAS45839.2020.9069041.
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31. J. Romero, N. Cuevas and E. Roa, “Energy Efficient Peripheral and System Buses for Low-Area and Low-Power SoC Applications,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 5, pp. 866-870, May 2020, doi: 10.1109/TCSII.2020.2984018.
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30. J. Ardila, H. Morales and E. Roa, “On the Cross-Correlation Based Loop Gain Adaptation for Bang-Bang CDRs,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 4, pp. 1169-1180, April 2020, doi: 10.1109/TCSI.2019.2952532.
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2019

29. L. E. Rueda G., J. S. Moya B. and E. Roa, “A Compact Industrial-Grade Multi-Threshold Brown-Out Detector,” 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genoa, Italy, 2019, pp. 923-926, doi: 10.1109/ICECS46596.2019.8964634.
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28. H. Gomez, J. Arenas, C. Rojas, D. Reyes, A. Mantilla and E. Roa, “A 6836ppmoC Tc 32.768Khz-To-1Mhz Rc-Based Oscillator With 726Pj Start-Up Energy,” 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-4, doi: 10.1109CICC.2019.8780374.
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27. J. Santamaria, N. Cuevas, G. L. E. Rueda, J. Ardila and E. Roa, “A Family of Compact Trim-Free CMOS Nano-Ampere Current References,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-4, doi: 10.1109/ISCAS.2019.8702294.
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26. A. Amaya, F. Castro and E. Roa, “Improving Low-Dropout Regulator Frequency Stability by Exploiting the Equivalent Series Resistor and Featuring an Adaptive Biasing Strategy,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702718.
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25. J. Ardila and E. Roa, “A Novel Loop Gain Adaptation Method for Digital CDRs Based on the Cross-Correlation Function,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-4, doi: 10.1109/ISCAS.2019.8702751.
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24. W. Ramirez and E. Roa, “Post-Silicon Debugging Platform with Bus Monitoring Capability to Perform Behavioral and Performance Analyses,” 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 81-84, doi: 10.1109/LASCAS.2019.8667537.
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23. L. Dovale, J. S. Moya and E. Roa, “A Programmable and Low-Area On-Die Termination for High-Speed Interfaces,” 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 173-176, doi: 10.1109/LASCAS.2019.8667552.
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22. W. Ramirez, H. Gomez and E. Roa, “On UVM Reliability in Mixed-Signal Verification,” 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 233-236, doi: 10.1109/LASCAS.2019.8667543.
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21. L. E. Rueda G., N. Cuevas and E. Roa, “An Ultra-Low Power Multi-Level Power-on Reset for Fine-Grained Power Management Strategies,” 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 185-188, doi: 10.1109/LASCAS.2019.8667574.
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20. N. Cuevas, J. Ardila and E. Roa, “An All-Thin-Devices Level Shifter in Standard-Cell Format for Auto Place-and-Route Flow,” 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 45-48, doi: 10.1109/LASCAS.2019.8667578.
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19. H. Morales, C. Duran and E. Roa, “A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller,” 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 97-100, doi: 10.1109/LASCAS.2019.8667579.
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18. H. Gomez, C. Duran and E. Roa, “Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage,” in IEEE Transactions on Consumer Electronics, vol. 65, no. 1, pp. 109-118, Feb. 2019, doi: 10.1109/TCE.2018.2890616.
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2018

17. A. Amaya, L. E. Rueda G and E. Roa, “A Multi-Level Power-on Reset for Fine-Grained Power Management,” 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Platja d'Aro, 2018, pp. 129-132, doi: 10.1109/PATMOS.2018.8464167.
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16. J. Ardila and E. Roa, “Stochastic resonance in bang-bang phase detector gain and the impact on CDR locking,” 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), Puerto Vallarta, 2018, pp. 1-4, doi: 10.1109/LASCAS.2018.8399933.
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15. A. Amaya and E. Roa, “On-Fly Offset-Correction Method for High-Speed Comparators using All-Digital Phase Measurement,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4, doi: 10.1109/ISCAS.2018.8351268.
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14. L. Fernandez, A. Amaya and E. Roa, “A 0.007mm2 50mA Three-Stage Fully-Integrated Capacitor-Less Low-Dropout Regulator,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4, doi: 10.1109/ISCAS.2018.8351678.
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13. H. Gomez, C. Duran and E. Roa, “Standard cell camouflage method to counter silicon reverse engineering,” 2018 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, 2018, pp. 1-4, doi: 10.1109/ICCE.2018.8326300.
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2017

12. C. Duran et al., “A system-on-chip platform for the internet of things featuring a 32-bit RISC-V based microcontroller,” 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), Bariloche, 2017, pp. 1-4, doi: 10.1109/LASCAS.2017.8126878.
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11. A. Amaya, J. Ardila and E. Roa, “A Digital Offset Reduction Method for Dynamic Comparators Based on Phase Measurement,” 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, 2017, pp. 661-664, doi: 10.1109/ISVLSI.2017.120.
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10. A. Amaya, H. Gomez and E. Roa, “Mitigating Row Hammer attacks based on dummy cells in DRAM,” 2017 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, 2017, pp. 442-443, doi: 10.1109/ICCE.2017.7889389.
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9. H. Gomez, O. Reyes and E. Roa, “A 65 nm CMOS key establishment core based on tree parity machines.” Integration 58 (2017): 430-437, doi: 10.1016/j.vlsi.2017.01.010
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2016

8. J. Ardila and E. Roa, “On the impact of channel loss on CDR locking,” 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016, pp. 1-4, doi: 10.1109/MWSCAS.2016.7870075.
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7. H. Gomez, A. Amaya and E. Roa, “DRAM row-hammer attack reduction using dummy cells,” 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), Copenhagen, 2016, pp. 1-4, doi: 10.1109/NORCHIP.2016.7792886.
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6. J. Cartagena, H. Gomez and E. Roa, “A fully-synthesized TRNG with lightweight cellular-automata based post-processing stage in 130nm CMOS,” 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), Copenhagen, 2016, pp. 1-5, doi: 10.1109/NORCHIP.2016.7792898.
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5. A. Amaya, H. Gomez and E. Roa, “A digital offset correction method for high speed analog front-ends,” 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), Belo Horizonte, 2016, pp. 1-4, doi: 10.1109/SBCCI.2016.7724077.
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4. H. G�1�71�1�77�1�71�1�77mez, �1�71�1�770�1�71�1�777. Reyes and E. Roa, “A fully synthesized key establishment core based on tree parity machines in 65nm CMOS,” 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, 2016, pp. 1-4, doi: 10.1109/PRIME.2016.7519517.
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3. A. Amaya, R. Villamizar and E. Roa, “An offset reduction technique for dynamic voltage comparators,” 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, 2016, pp. 1-4, doi: 10.1109/PRIME.2016.7519549.
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2. C. Duran et al., “A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC,” 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), Florianopolis, 2016, pp. 315-318, doi: 10.1109/LASCAS.2016.7451073.
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1. E. G. Carre�1�71�1�770�1�71�1�779o et al., “A 3.9 compression-ratio Huffman encoding scheme for the large ion collider on 65nm and 130nm CMOS technologies,” 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), Florianopolis, 2016, pp. 347-350, doi: 10.1109/LASCAS.2016.7451081.
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