High-Speed Interface

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Several high-speed links applications incorporate CDR circuits at the receiver end (RX). USB3.1, PCIexpress and serial advanced technology attachment (SATA) are examples of those applications. Digital phase-locked loop (DPLL) based CDR is widely used due to its power efficiency, flexibility and effective functionality for Gb/s data links over analog counterparts. Addressing the design of a DPLL-based CDR requires clear understanding and proper simulation of the basic equivalent linear models. We are focused on the RX block, specially on CDR and slicer circuits for USB3.1 standard. We have designed and taped-out a high-speed slicer with an alternative offset-reduction technique in 130nm.

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CTLE

We are developing a comparative study of the topologies of continuous time linear equalizers that reduce the ISI caused by the communication channels in high speed interfaces. This study is particularly focused on the development of equalizers which operate at speeds greater than 5GHz, allowing data rates above 10Gbs. We are searching the best trade-off between power consumption, gain boosting, linearity and area.