Analog/Mixed-signal and RF design engineer with comprehensive academic background in VLSI design.
- Strong background on analog and digital IC design flow and techniques.
- Strong knowledge of IC design flow using commercial tools and product cycle.
- Hands-on experience with broad range of CMOS process nodes, 28nm, SOI 45nm, 65nm, 0.13um, 0.18um, 0.35um.
- Solid experience on Cadence analog design flow environment.
- Experience on Cadence-EDI digital design flow environment.
- Experience on IP verification using Verilog-AMS, Verilog, System Verilog and cosim-MATLAB.
- SERDES blocks: TX pre-emphasis, driver, T-coil and termination, ESD, CTLE, DFE and 2nd-order digital CDR.
- Strong team player with leadership qualities and ability to work independently.
- Experience developing Standard Cell Libraries from design to final application.
- Convex optimization techniques to speed-up the design of circuits.